1. Field of the Invention
This invention relates to a semiconductor device in which a non-volatile semiconductor memory cell portion and a logic portion comprising two or more-layered metal layers are formed on a single semiconductor substrate, and more particularly to a semiconductor integrated circuit having an erasable and programmable read only memory (EPROM) as the non-volatile semiconductor memory cell.
2. Description of the Related Art
In the prior art, a semiconductor integrated circuit device employing an EPROM is used as a semiconductor device having a semiconductor substrate, and a non-volatile semiconductor memory cell portion and a logic portion formed on the substrate.
In a semiconductor integrated circuit device of this kind, the logic portion has been developed to have multi-layered aluminum (Al) wirings in accordance with the high-integration/advanced-function tendency of the device. On the other hand, the memory cell portion (EPROM) comprises of a single Al layer in many cases, since the degree of integration is little increased by multi-layered wiring employed therein. Thus, a logic portion with two or more-layered Al wires, a memory cell portion with a single Al wire, and an I/O portion which surrounds the logic portion and the memory cell portion are formed on a single semiconductor substrate.
Further, the capacity of the EPROM has recently been increased, and the memory cell portion has been occupying more than half of the area of the semiconductor integrated circuit device.
The structure of the memory cell having a single Al wire layer will now be explained in more detail.
FIG. 1 is a cross sectional view of the memory cell portion.
As is shown in FIG. 1, the memory cell portion comprises field oxide films 101 selectively formed on a semiconductor substrate 100, floating gates 103 each formed between a corresponding adjacent pair of the field oxide films 101 with an insulating film 102 interposed therebetween, a word line 104 of polysilicon formed on the above elements with an insulating film therebetween, single-layered Al wires 106a and 106b on the word line 104 with an interlayer insulating film 105 therebetween, and a passivation film 107 protecting the surface of the device.
The Al wire 106a is a bit line connected to a drain diffusion layer (not shown) via a drain contact, and the Al wire 106b is a source line connected to a source diffusion layer (not shown) via a source contact.
In a semiconductor integrated circuit device having the memory cell portion with the single-layered Al wires 106a and 106b and a logic portion comprising two or more-layered Al layers, the second and subsequent-layered Al layers of the logic portion are liable to become thinner than its first Al layer for the following reasons.
In general, Al wires are formed by selectively etching an Al layer. This etching is influenced by the coating ratio of a photoresist pattern used as a mask to the Al layer. The lower the coating ratio of the photoresist pattern (i.e., the mask pattern), the greater the Al wire is etched due to undercut. This is because if the coating ratio is low, only a small amount of a carbon compound is supplied from the resist pattern into the Al layer during the RIE (Reactive Ion Etching), with the result that lateral-directional etching or isotripic etching of the Al layer is performed.
Since the memory cell portion does not have second and subsequent-layered Al wire layers, the coating ratios of the resist patterns to the Al layers to be selectively etched are very low at the time of selectively etching the Al layers to form Al wires of second and subsequent-layered layers of the logic portion. Accordingly, the amount of a carbon compound to be supplied from the resist pattern into the Al layers are greatly reduced, and it is highly possible that the Al layers are thinned.
In general, to prevent a metal layer, such as the Al layer, from being thinned, a dummy mask pattern, which is used only to increase the coating ratio, is formed on that portion of the metal layer, at which the coating ratio of a resist pattern to the metal layer is low, in order to increase the coating ratio. Alternatively, a simple line/space pattern is manually provided on the metal layer so as to increase the coating ratio.
However, these dummy patterns for increasing the coating ratios may well reduce the transmittance of ultraviolet ray and hence cause erase-fail of data in a semiconductor integrated circuit device with an EPROM. Thus, the dummy patterns cannot be formed on the memory cell portion.
As described above, it is very difficult to form, on the memory cell portion, a pattern which can maximize the coating ratios of the resists to the second and subsequent-layered metal layers of the logic portion, and at the same time can minimize a reduction in the transmittance of ultraviolet ray. Therefore, the conventional approach to increase the coating ratios cannot be employed to prevent the second and subsequent-layered Al layers of the logic portion from becoming thin.